1. Field of the Invention
The present invention relates to packaging of integrated circuits for vertically integrated hybrid components in the form of a wafer level package.
2. Description of the Related Art
Vertically integrated hybrid components generally include multiple different elements, which are assembled one above the other as a stack or chip stack. The different functionalities of the elements supplement one another advantageously to yield an application. Depending on the application, MEMS elements having a micromechanical functionality and also ASIC elements having a plain circuitry-wise functionality may be combined with one another in one component. ASIC elements are also frequently used for capping the micromechanical structure of a MEMS element as part of vertically integrated hybrid components. For example, there are known vertically integrated hybrid inertial sensor components including a micromechanical sensor element and an ASIC element on which the analyzer circuit for the sensor signals is integrated. In these inertial sensor components, the ASIC element is assembled over the sensor structure of the MEMS element and seals it off from environmental influences.
In the case of wafer level packages, the individual element substrates are processed largely independently of one another to implement the corresponding circuitry-wise and/or micromechanical functionality for a plurality of elements. The element substrates are then assembled in the wafer composite and are also contacted electrically. Only thereafter are the packages separated. This very extensive parallelization of chip manufacturing and packaging is extremely efficient with regard to the manufacturing process and the manufacturing costs. Furthermore, the component size may thus be minimized. Such packages require very little circuit board space and have a very small overall height. This miniaturization in both area and height has opened up a variety of possibilities for the development of novel and improved end products.
The electrical connection between the individual elements of a vertically integrated hybrid component and also its external contacting frequently take place in practice with the aid of vias. The implementation of such vias in the individual element substrates of a vertically integrated hybrid component is generally associated with complex structuring methods and coating or filling of structures with a very high aspect ratio. These processes increase the manufacturing complexity and consequently also have definite effects on the manufacturing costs.